1. Field of the Invention
The present invention relates to direct digital frequency synthesis, and more particularly, to a direct digital frequency synthesizer using a hybrid digital to analog converter, which is capable of synthesizing an analog signal with high quality without base decoding, thereby providing improved size and efficiency, and a synthesizing method thereof.
2. Description of the Related Art
With the necessity of high speed processing systems with advance of information & communication technologies, there is an increasing need of high speed digital frequency synthesis systems which are capable of synthesizing a desired frequency at a high speed with minimal latency.
In general, a frequency synthesis system includes a direct frequency type and an indirect frequency type. The indirect frequency type, such as a phase locked loop (PLL) frequency synthesizer, requires a voltage controlled oscillator (VCO), thereby producing phase noises, and has a feedback loop, thereby providing great latency for frequency synthesis. For the purpose of overcoming this problem, there have been mainly used direct digital frequency synthesizers with small latency for frequency synthesis, small phase noise, and for precise and high speed frequency synthesis.
Since a direct digital frequency synthesizer (DDFS) is capable of instantaneous phase and frequency conversion over a wide band and provision of correct phase and frequency without signal discontinuity owing to a merit of digital processing, it is suitable for high speed precise frequency synthesis and is mainly applied to radars and wireless communications requiring regular high agility frequency hopping. The direct digital frequency synthesizer has an increasing application range to various fields for applications by simplifying its hardware configuration and hence reducing production costs. In addition, since portions except for a digital to analog converter (DAC) are implemented by digital circuits, use of DDFSs is on the rise with increase of integration of semiconductor integrated circuits.
FIG. 1 shows a general DDFS configuration. As shown, a DDFS includes a phase accumulator 10 for accumulating frequency control words (FCWs) to generate new phase data for each segmented clocks with phase angles (0 to 2p) around a circle through overflow, a phase to amplitude mapper (PAM) 20 for discretely mapping the phase data provided by the phase accumulator 10 onto amplitudes corresponding to sine waves, and a digital to analog converter (DAC) 30 for converting discrete amplitudes provided by the PAM 20 into an analog signal having a desired frequency form.
Methods of mapping phase onto amplitude in the PAM 20 may include, for example, a method of using a read only memory (ROM), a method of using Taylor series, a method of using a coordinated rotation digital computer (CORDIC), etc.
Although the method of using ROM provides various schemes for size reduction, this method is still low in space efficiency and has additional complicated circuits for size reduction, thereby consuming much power. Therefore, the method of using Taylor series or the method of using CORDIC has been indeed used to minimize the use of ROM.
However, both of the method of using Taylor series and the method of using CORDIC require a very complicated operation configuration and still a ROM of a look-up table scale, thereby still raising a problem of high power consumption and delay due to complexity without providing particular integration efficiency.
To overcome this problem, there has been recently proposed a DDFS structure having a relatively less complicated control configuration without using a ROM. For example, U.S. Patent publication No. US20070174371 discloses a hardware-efficient phase-to-amplitude mapping design for direct digital frequency synthesizer using a method of configuring a PAM for converting a FCW into a binary code having amplitude of a sine waveform and a DAC for converting the binary code into a sine wave.
FIG. 2 shows a DDFS configuration disclosed in U.S. Patent publication No. US20070174371. As shown, a DDFS includes a PAM 40 to receive a 14-bit output provided from a phase accumulator, and a linear DAC 50. The PAM 40 is configured to use 5 bits, which are some of the output, to set base points to set a basic position of amplitude with low resolution, 7 bits, which are some of the output, to set an extension amplitude value for linear approximation in conformity to a sine waveform between base points, and 2 bits, which are the remaining of the output, to extensionally map a ¼ sine wave amplitude accordingly obtained onto a sine wave of one period as a whole. The linear DAC 50 is configured to convert a single binary value for the sine wave amplitude output from the PAM 40 into an analog value.
Although the linear DAC 50 may be configured as a single linear DAC in which the shown entire 12 bits have a binary weight, the hardware configuration may be simplified by configuring some upper bits to be processed by a linear DAC 51 applying a thermometer decoder and configuring the remaining lower bits to be processed by a DAC 52 to which a binary weight is applied. It is here noted that the bits divided and processed by the PAM 40 are independent of the internal DAC configuration bits of the linear DAC 50.
The PAM 40 operates to map phase data output from the phase accumulator onto binary values of a precise sine waveform. Specifically, of the data of 14 bits provided by the accumulator, the upper 2 bits are used to control operation of a first complementor 41 and a second complementor 46 for specifying a position of the ¼ sine wave amplitude on a 4-quadrant, the next upper 5 bits are analyzed by a base decoder 42 when then outputs information of 12 bits to specify base points which are positions of base amplitudes having low resolution. A controller 43 uses the next upper 5 bits to generate a 16-bit signal for generating predetermined gradients for linear approximation between the base points and a 4-bit signal for specifying a combination of addition or subtraction of the generated gradients. A gradient generator 44 uses the lower 7 bits of the 14-bit data provided by the phase accumulator and the 16-bit signal provided by the controller 43 to generate 8 kinds of different gradients (by using T-Term blocks). A 12-bit operator 45 carries out an operation for the 4 of the 8 kinds of 8-bit gradient values provided by the gradient generator 44, the combination information of the gradient values provided by the controller 43, and the 12-bit base point information provided by the base decoder 12 to output 11-bit binary information on amplitude. The second complementor 46 outputs an amplitude for a complete entire sine wave phase of the total of 12 bits having shifting information on top and bottom positions of the amplitude, included in one most significant bit, as binary values.
In the end, the above method is a method of setting positions of base amplitudes having low resolution by means of the base decoder 42 and approximating a gradient interconnecting points between the set base amplitudes (that is, coarse segments for amplitude) by combining a plurality of gradient values, thereby generating final binary information in the PAM in consideration of all of them.
Although the above-described method may configure a DDFS with no ROM, it requires pipelines of a considerable size for high speed operation and still has a problem of configuration of complicated operators. In addition, since an output of PAM has a binary value for designation of single amplitude, its resolution is fixed at the set number of bits.
That is, as shown, a considerably complicated logic configuration is required for the base decoder 42 for obtaining base points, and 12-bit pipelines are required for its output. In addition, the 12-bit operator 45 having the same size as output bits of the base decoder 42 is required for operation of such base points and gradients, and also pipelines are required accordingly, which results in complexity of configuration. Such complexity of configuration leads to low integration, high costs, high power consumption and operation delay. Accordingly, such an existing complicated configuration has to be simplified for expansion of an application range of DDFS.
In the end, there is a need of DDFS of a new form which is capable of increasing integration, saving power and maintaining or improving output quality by overcoming such configuration complexity and simplifying a configuration of PAM, which occupies most of an actual total area, to decrease its area.